Compilation pour cibles hétérogènes : automatisation des analyses, transformations et décisions nécessaires

8 pagesInternational audienceLes accélérateurs matériels, telles les cartes FPGA ou les cartes graphiques, apportent une alternative ou un complément intéressant aux processeurs multi-coeurs classiques pour de nombreuses applications scientifiques. Il est cependant coûteux et difficile d'y porter des applications existantes ; et les compilateurs standards, traditionnellement portés sur la génération de code pour processeurs séquentiels, ne disposent pas des abstractions nécessaires à la génération automatique et re-ciblable de code pour ces nouvelles cibles. Cet article présente un ensemble de transformations de code de haut niveau reposant sur une abstraction à plusieurs niveaux de l'architecture des accélérateurs actuels et permettant de construire des compilateurs spécifiques à chaque cible en se basant sur une infrastructure commune. Ces transformations ont été utilisées pour construire avec PIPS deux compilateurs complètement automatisés pour un processeur embarqué à base de FPGA et pour GPU NVIDIA avec PAR4ALL

Activity Counter: New Optimization for the Dynamic Scheduling of SIMD Control Flow

Abstract SIMD or vector computers and collection-oriented languages, like C , are designed to perform the same computation on each data item or on just a subset of the data. Subsets of processors or data items are implemented via an activity bit and a stack of activity bits when subsets of subsets are supported. This method is also used in VLIW processors through if-conversion to implement parallel control flow as in SIMD computers. We present a new method of dynamic sheduling of several SIMD control flow constructions which can be nested. Our implementation of activity stacks is based on activity counters. At a given stack depth n, the number of memory bits required is log 2 n, whereas previous implementations require n bits. The local controller is of equivalent complexity in both cases. This algorithm is useful for SIMD, vector or VLIW machines and for compilers of collection-oriented languages on MIMD computers

PyPS a programmable pass manager

International audiencePIPS4U :1- Complex Environment2- Source-to-Source3- Model for Code Transformations4- Based on a Scripting Language5- Abstractions6- Control Structures7- Target

Polyèdres et Compilation

22 pagesInternational audienceLa première utilisation de polyèdres pour résoudre un problème de compilation, la parallélisation automatique de boucles en présence d'appels de procédure, a été décrite et implémenté il y a près de trente ans. Le modèle polyédrique est maintenant reconnu internationalement et est en phase d'intégration dans le compilateur GCC, bien que la complexité exponentielle des algorithmes associés ait été pendant très longtemps un motif justifiant leur refus pur et simple. L'objectif de cet article est de donner de nombreux exemples d'utilisation des polyèdres dans un compilateur optimiseur et de montrer qu'ils permettent de poser des conditions simples pour garantir la légalité de transformations

Ametsa : a generic home control system based on UPnP

International audienceHome services are gaining more and more interest in the computer science community. In particular, several service discovery systems (SDS) have been proposed that assume the presence of devices interpreting standard and open Internet protocols. However, the lack of home devices understanding such protocols has restricted the proliferation of control applications at home and the utilization of such systems is limited to computer science environments. The "Maison Intelligente" project aims at proposing generic services to control home devices based on SDS in order to ensure the independence from devices manufacturers. We have first developed the Ametsa service which exploits the UPnP SDS in order to be aware of arrival or removal of devices and to send or receive commands to/from available devices. We also propose gateways to connect UPnP to some other protocols. Some experiments have already been performed based on a prototype consisting on Ametsa and two gateways allowing the control of X2D and X10 devices

A single-source C++20 HLS flow for function evaluation on FPGA and beyond

International audienceThis paper presents a framework to reuse the intelligence of RTL generators in a single-source HLS setting. This framework is illustrated by a C++ fixed-point library to generate mathematical function evaluator. A compiler flow from C++20 to Vivado IPs has been developed to make the library usable with Vitis HLS. This flow is demonstrated on two applications: an adder for the logarithmic number system, and additive sound synthesis. These experiments show that the approach allows to easily tune the precision of the types used in the application. They also demonstrate the ability to generate arbitrary function evaluator at the required precision

PIPS Is not (just) Polyhedral Software Adding GPU Code Generation in PIPS

6 pagesInternational audienceParallel and heterogeneous computing are growing in audience thanks to the increased performance brought by ubiquitous manycores and GPUs. However, available programming models, like OPENCL or CUDA, are far from being straightforward to use. As a consequence, several automated or semi-automated approaches have been proposed to automatically generate hardware-level codes from high-level sequential sources. Polyhedral models are becoming more popular because of their combination of expressiveness, compactness, and accurate abstraction of the data-parallel behaviour of programs. These models provide automatic or semi-automatic parallelization and code transformation capabilities that target such modern parallel architectures. PIPS is a quarter-century old source-to-source transformation framework that initially targeted parallel machines but then evolved to include other targets. PIPS uses abstract interpretation on an integer polyhedral lattice to represent program code, allowing linear relation analysis on integer variables in an interprocedural way. The same representation is used for the dependence test and the convex array region analysis. The polyhedral model is also more classically used to schedule code from linear constraints. In this paper, we illustrate the features of this compiler infrastructure on an hypothetical input code, demonstrating the combination of polyhedral and non polyhedral transformations. PIPS interprocedural polyhedral analyses are used to generate data transfers and are combined with non-polyhedral transformations to achieve efficient CUDA code generation